how to test a solid state relay

Like other advanced I/O schemes, RapidIO abandons simple andhierarchical buses and opts instead for a switched fabric ofpoint-to-point connections. The switching devices employ alow-latency packet-switching scheme to handle multiple data streamssimultaneously, increasing data flow rates to multiples of the bustransfer speed.

View an example here .

how to test a solid state relay

The reason for moving to a switched architecture is simple.Shared multi-drop buses have already been exploited to their fullpotential. Such techniques as increasing clock frequencies,widening the interface, pipelining transactions, splittingtransactions, and allowing out-of-order execution have becomeincreasingly expensive and are showing diminishing returns. So theRapidIO architecture employs a point-to-point, moderately parallel,packet-based interconnect. Other I/O schemes using aswitched-fabric include Mercury computer's RACEway (from whichRapidIO was partially derived), and the proposed InfiniBandarchitecture (that primarily targets LAN, SAN and WAN connectionsat the server level). Packet switching has also found increasinguse for advanced I/O, for example, in SKY Computers'SKYchannel.

RapidIO is specified as a three-layer architectural hierarchy.The top level defines the overall protocol and packet formats toallow end points to process transactions. A transport specificationprovides the necessary route information for a packet to move fromend point to end point. Finally, a physical specification containsthe device-level interface such as packet transport mechanisms,flow control, electrical characteristics, and low-level errormanagement.

how to test a solid state relay

Figure 2 : The physical interface is where RapidIO shines.As part of its performance-boosting strategy, RapidIO uses LVDS(low-voltage differential signaling) for the electrical interface,primarily for backplane applications (linking pairs of connectors).LVDS is a proven technology that already enhances the performanceof other I/O schemes (such as the Ultra SCSI bus) and has beenstandardized as IEEE 1596.3. In addition to boosting data rates,LVDS (with a 200-450mV swing) can lower power consumption. It is,however, restricted to short transmission distances (30 inches oftrace on a standard circuit board).

LVDS allows RapidIO to promise significant interconnectbandwidth. The initial version of RapidIO will use an 8-bit channelwith a 250-MHz clock. Signals are source-synchronous, however, sothat RapidIO will operate in a multiple-clock environment. Datasampling occurs on both edges of the clock signal so that theresulting data rate 2 GB/s. Future implementations will includeboth 8-bit and 16-bit versions, providing data that can scale to 4GB/s for the 16-bit interfaces.

how to test a solid state relay

In addition to its performance and cost advantages, RapidIO hasthe advantage of relative simplicity compared to otherhigh-performance I/O schemes. Rick O'Connor, VP of TundraSemiconductor (Kanata, Ont.) explains, RapidIO is just messagepassing in a memory-mapped environment with the same load-storeprogramming model people are used to with standard buses.” As aresult, the RapidIO scheme can be used without altering operatingsystem software, and it needs no special device drivers. Thearchitecture is also transparent to application software. So far assoftware is concerned, RapidIO interconnects look like atraditional microprocessor and peripheral bus. That simplicity andcompatibility with older architectures should speedtime-to-market.

How RapidIO Competes

Using deep memory and Agilent's MegaZoom technology, the transmitted data packet can be examined in fine detail without retriggering. The initial signal transitions, which were captured at a timebase setting of 1 mill isecond/division, now can be zoomed to 5 microseconds/division. Often, intermittent anomalies may be captured in a big-picture view, but when the signal is recaptured, the anomaly is no longer present. The ability to trigger one time with deep memory allows a large time capture so that signal behavior can be viewed in detail later.

A packet is a single bundle of information transmitted within a piconet. The packet is transmitted on a frequency hop and nominally covers a single time slot, but may be extended to cover up to five time slots.

The first two pulses correspond to the Bluetooth packet preamble, consisting of a fixed zero-one pattern of four binary symbols. The preamble is the first part of the packet access code. Immediately following the preamble is a pattern of ones and zeros comprising the sync word.

Since the preamble is predefined, the bit size can be determined by inspection. Once the bit size is known, the entire bit stream, encompassing the access code, header and payload, can be identified bit-by-bit. MegaZoom lets designers view the high-level transactions to verify that the operation is correct. Users can pan and zoom through the data packet to verify specific bit-stream data values.

A variation would be to use four channels to probe the transmit and receive signals of both Bluetooth devices simultaneously. That lets designers pan and zoom through the acquisition to view correlated waveform activity between the two Bluetooth devices. The technique is useful, for example, to verify that a synchronous-connection-oriented (SCO) link between Bluetooth applications is functioning. An SCO link is a direct, dedicated bandwidth connection for use with time-critical applications such as voice. The verification can identify connectivity errors when integrating two Bluetooth devices into one system.

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