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The software analyzes any one of the up to four transmit antenna ports defined for the LTE downlink transmitter. Auto-detection of downlink data-burst allocations is also supported, along with manual entry of data bursts and auto-recall of Agilent Signal Studio setup files. For LTE uplink, the signal analysis solution supports half sub-carrier shift as defined by the 3GPP standard, also said to be a unique capability of Agilent.

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The software analyzes any one of the up to four transmit antenna ports defined for the LTE downlink transmitter. Auto-detection of downlink data-burst allocations is also supported, along with manual entry of data bursts and auto-recall of Agilent Signal Studio setup files. For LTE uplink, the signal analysis solution supports half sub-carrier shift as defined by the 3GPP standard, also said to be a unique capability of Agilent.

IMEC's main partners in the 32-nm and sub 32-nm process project include Infineon Technologies, Qimonda, Intel, Micron, NXP, Panasonic, Samsung, STMicroelectronics, Texas Instruments and TSMC, and IMEC’s key CMOS partners including Elpida and Hynix.

The researchers said the low threshold voltage (Vt) was achieved by applying a thin dielectric cap between the gate dielectric and metal gate. In addition, the use of laser-only annealing for gate stack engineering resulted in a significant reduction” of the minimum sustainable gate length and improved short-channel effect control.

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The same processes were applied on FinFETs and resulted in a possible candidate technology for the 22-nm node.

A major challenge in using high-k dielectrics for CMOS devices is the high threshold voltage resulting in low performance. Dual metal gates in combination with dual dielectrics can solve this problem but have the drawback that extra processing steps are required resulting in a higher processing cost.

IMEC developed a simpler, lower-cost integration scheme using only one dielectric stack and one metal. A thin dielectric cap is deposited between the gate dielectric and metal gate which effectively modulates the work function towards the optimal operating zone. Laser anneal instead of spike anneal is applied to reduce the effective oxide thickness.

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The researchers used both a lanthanium- (La2O3) and dysprosium-based (Dy2O3) capping layer for nMOS and an aluminum-based capping layer for pMOS. Symmetric low Vt of +/-0.25V was achieved and drive currents of 1035µA/µm and 505µA/µm for nMOS and pMOS respectively at VDD of 1.1V and Ioff of 100nA/µm. Successful CMOS integration was illustrated by a ring oscillator delay of less than 15ps.

The team has also developed a time-dependent dielectric breakdown model to predict accurately the reliability of the devices. The model is based on the statistical analysis of hard breakdown including multiple soft breakdown and wear out. By applying the model on the high-k/metal gate devices, they say they demonstrated the excellent” quality of the gate dielectrics.

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Working closely with NXP Semiconductors and TSMC, the researchers managed to record excellent performance” (drive current of 950µA/µm and Ioff of 50nA/µm at VDD of 1V for nMOS FinFETs) and short channel effect control for tall, narrow FinFETs without mobility enhancement.

Teams also compared physical vapor deposition (PVD) and atomic layer deposition (ALD) and reported that PVD of titanium nitride (TiN) electrodes on hafnium oxide (HfO2) dielectrics gave improved nMOS performance compared to ALD TiN.

Displays for other applications that are typically priced at the spot rate, like digital photo frames and portable DVD players, were up quarter-on-quarter, reflecting the growing trend away from bargain pricing of 7 and 8 inch displays.

DisplaySearch (Austin, TX.) also suggests that digital cameras, with ASPs that generate the lowest revenue/sq. m, increased by 1 to 4 percent in Q3 over the second quarter, and are expected to be flat in Q4.

The firm forecasts overall ASPs to be down 1 percent in the fourth quarter, but up 2 percent in the first quarter of 2008.

DisplaySearch suggests that on a year-on-year basis, ASP reductions are reaching bottom, with a 5 percent decline and 2 percent increase forecasted for Q4'07 and Q1'08, respectively.

On a weighted average basis, ASPs were $8.92, flat Q/Q, but down 16 percent year-on-year. By technology, weighted ASPs for a-Si TFT LCDs and CSTN LCDs — which make up 50.1 percent of small/medium display shipments — were both down 7 percent Q/Q, and down 17 percent and 23 percent respectively year-on-year.

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