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The ‘Ready for IBM Technology’ mark identifies solutions that have been pre-tested and validated for compatibility with IBM Microelectronics’ products and services by solution developers.

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The ‘Ready for IBM Technology’ mark identifies solutions that have been pre-tested and validated for compatibility with IBM Microelectronics’ products and services by solution developers.

Mistry said Intel's work on FUSI metal gates with a silicon dioxide, presented at IEDM, showed that the work function for the PMOS transistor is not good enough. We would have to improve on FUSI to make it a competitive approach.”

IBM, for its part, does not have FUSI on its road map, according to Gary Bronner, an IBM project leader at the IBM-AMD alliance based in East Fishkill, N.Y.

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IBM has done a lot of work on FUSI, but it is not on our list of options,” he said in an interview.

Stretching strainIn lieu of FUSI, some companies are emphasizing strain engineering. Strained silicon, first introduced by Intel at the 90-nm node, has been adopted by many other chip makers at 65 nm. The results have been startling, said Mark Pinto, chief technology officer at Applied Materials Inc., with PFET performance boosted by nearly 100 percent from the unstrained 130-nm node to the fully strained 65-nm node. The electron carriers in the NFET responded to tensile strain with a 50 percent boost in mobility.

Strain is the best of what we've got in our toolbox right now,” Pinto said.

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At IEDM, technologists from a Toshiba-Sony research group presented data showing that strain techniques may continue to work their magic at 45 nm. The Sony-Toshiba team concluded that stress techniques are scalable for future technologies,” said A. Oishi, an engineer working at Toshiba Corp.'s system-on-chip R&D center in Yokohama, Japan.

Yale University professor T.P. Ma noted, however, that overall results indicate diminishing returns” at the 45-nm node. Silicon is already under a very large strain — the lattice is stretched [on the NFET] or compressed [on the PFET] by about 1 percent,” Ma said.

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In one sense, shrinking the device is a friend of strained silicon: As the channel length shrinks, the smaller amount of silicon is easier to bring under strain. But scaling also means there is less space to deposit the germanium atoms, which exert a compressive stress on the silicon lattice in the PFET. The nitride capping layers also take up space.

As MIT professor Gene Fitzgerald explained, the higher strain can cause dislocation issues that some process engineers haven't had to deal with in 30 years.”

The new power amplifier delivers superior performance through channel matching, maximizes efficiency with on-chip power detection, and lowers bill-of-material costs by eliminating several external components.

A variety of MIMO products have emerged to address consumer demand for greater wireless performance and to support advanced multimedia applications,” said Frank Chang, vice chairman and chief technical advisor, SST Communications. Our dual power amplifier is the first to help wireless system designers maximize the throughput and range of their MIMO products without a significant impact on design costs. As the industry moves closer to the 802.11n standard, we will continue to enable our customers to capitalize on this growing market by delivering cutting-edge power solutions for the 2.4 and 5 GHz bands.”

The SST12LP30 power amplifier provides factory-matched gain and output power (within 0.5dB) on two parallel channels. By eliminating possible power/gain incompatibilities, channel matching can improve performance, reduce engineering time and enable higher-yield production of MIMO devices. To further improve performance, the SST12LP30 provides 20dB of isolation between the two channels, which reduces interference and maintains signal quality for each independent data stream.

The SST12LP30 also features dual on-chip power detectors that not only increase amplifier efficiency and reliability, but also eliminate costly components such as Schottky diode detectors and directional couplers. The built-in power detectors provide a large dynamic range of 20 dB – with dB-wise linearization and high stability over temperature (

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