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Robert J. Lepofsky, president and CEO of Brooks, painted a mixed picture. ''Our results for the quarter were in the middle of the range of guidance provided earlier but are still below the level of performance we are aiming to achieve in the short term,'' he said in a statement.

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Robert J. Lepofsky, president and CEO of Brooks, painted a mixed picture. ''Our results for the quarter were in the middle of the range of guidance provided earlier but are still below the level of performance we are aiming to achieve in the short term,'' he said in a statement.

The CEA clearly stated that it owns the patents. Soitec is the exclusive licensee.

Through this action, the CEA and Soitec (Bernin, France) said they expect a permanent injunction against MEMC's use of the patented technologies and monetary damages for infringement.

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SAN JOSE, Calif. — Seeking to meet exploding demand, SunPower Corp. plans to build its third solar cell fabrication plant in Malaysia.

Until now, SunPower's production plants have been located exclusively in the Philippines.

The Malaysian plant, dubbed Fab 3, is expected to have an annual capacity in excess of 1-gigawatt when completed. Solar cell production in Fab 3 is likely to begin in 2010, with the integrated site development planned to start later this year.

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''The new manufacturing facility is expected to be constructed in two phases, with the first phase comprised of 14 solar cell production lines with a nameplate capacity of 40 megawatts each,'' according to San Jose-based SunPower. ''After completion of phase two, at a scale in excess of 1-gigawatt, Fab 3 is estimated to achieve materially lower capital cost per watt compared to SunPower's Fab 1 and Fab 2.''

The scale and breadth of our Fab 3 campus in Malaysia will be a core element of our technology and manufacturing roadmap that drives us to our 50 percent cost reduction plan by 2012,” said Tom Werner, CEO of SunPower, in a statement.

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At present, SunPower makes its solar cells in the Philippines. It currently operate seven cell manufacturing lines, with a total rated manufacturing capacity of approximately 214 megawatts per year.

By the end of 2008, we plan to operate 12 solar cell manufacturing lines with an aggregate manufacturing capacity of 414 megawatts per year, according to SunPower's recent filing.

A fundamental challenge in view of technology scaling is to achieve sufficient analog performance (noise, linearity) under ever decreasing supply voltages. As the analog headroom diminishes, the design of ADC internal analog blocks such as op-amps, reference generators, input- and reference buffers become increasingly difficult.

Selecting a suitable ADC architecture that will survive migration over several generations of CMOS technology is therefore a matter of finding an architecture with minimal analog content. In particular it is desirable to minimize the amount of amplifiers in the design. Buffer amplifiers and op-amps used in the signal path are required to have a certain performance over the internal full-scale range of the design. With shrinking headroom this can be a real challenge.

Comparators are usually less of a problem since they don't need to accurately convey a signal with a certain swing. Rather, they are only required to accurately detect the polarity of a signal ” something that can be done with a much more limited swing. Nevertheless, comparators are analog blocks that contribute to the overall power dissipation. The amount of comparators should therefore still be minimized.

It will be shown below that architectures with less analog content also tend to achieve the best power/performance ratios.

Current high-speed ADCs are typically pipeline, flash or folding designs that utilize the inherent high-speed potential of the underlying architecture, or parallel time-interleaved ADCs that overcome the inherent speed-limitation of the ADC core by means of parallelism. An example of the latter is Sicon Semiconductors A/Dvance I and A/Dvance II range of parallel SAR (PSAR) ADCs.

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