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Virtual concatenation and LCAS rely on several VT or TU containers to distribute the 10- or 100-Mbit/s Ethernet signal evenly over many lower rate tributaries. For example, a single 10-Mbit/s Ethernet signal can be spread out over seven VT1.5 containers and each VT container may be cross connected through the network independent of the other six VTs. All VTs are re-ordered and then consolidated at the receiving end to rebuild the original 10 Mbit/s Ethernet signal.

SG73S2BTTD10R5D_Datasheet PDF

Virtual concatenation and LCAS rely on several VT or TU containers to distribute the 10- or 100-Mbit/s Ethernet signal evenly over many lower rate tributaries. For example, a single 10-Mbit/s Ethernet signal can be spread out over seven VT1.5 containers and each VT container may be cross connected through the network independent of the other six VTs. All VTs are re-ordered and then consolidated at the receiving end to rebuild the original 10 Mbit/s Ethernet signal.

CAM is often used to improve packet-classification performance, although pipeline stages may be needed if there is not enough CAM to hold an adequate set of packet headers, or if the memory is not wide enough to hold entire headers. SDRAM can be used instead of SRAM when the RAM size makes the cost of SRAM prohibitive.

Communication tasks often need memory with odd data-type sizes. For example, packet-classification algorithms use data types that are tens of bytes wide to store packet headers. In such cases, the use of commercial memory chips, which are designed for standard data types, may result not only in low bandwidth but also in unused parts of each memory chip. Embedded CAM memory may be a better choice.

SG73S2BTTD10R5D_Datasheet PDF

Embedded memories can be large (several megabytes) and fast (300 to 400 MHz, single cycle) with data paths in the hundreds of bits. When parts of packets are processed only by one block, such as a mapping function, that block can have a dedicated memory, sized according to its task. For large packets, a single multi-port memory can service multiple processing blocks. FEC is a candidate for this configuration. Single-ported memories, however, run faster and use less power than equivalent-sized multi-ported memories.

System-Level Design Methodology The challenges of designing complex, high-speed chips require the use of a hierarchical, system-level design flow that moves from system concept, to functional specification, to executable specification of an implementation-independent architecture, to register-transfer-level (RTL) chip design, with functional and standards-compliance verification being done in parallel. This approach reduces the complexity and time required for design and verification by allowing modeling, co-simulation, and verification to begin as early as possible in the design cycle. Simulation speeds of several hundred-thousand cycles per second can be achieved with executable architectural specifications.

Based on a chip's functional specification, an executable specification can be developed in the SystemC language using the transaction-level modeling (TLM) technique, which models events (such as interrupts) and exchanges of data (such as register or memory accesses). Under this approach, an untimed specification is first developed, in which event ordering is specified but without timing values. Then, the untimed specification is refined to a timed specification, in which events are assigned latencies and initiation intervals.

SG73S2BTTD10R5D_Datasheet PDF

Running simulations with the timed executable specification reveals system bottlenecks and provides quantitative data on how to improve the system architecture. It also supports rapid exploration and validation of architectural alternatives, in the quest for optimal system performance. Existing RTL models can be verified together with the SystemC executable specification enabling the reuse of existing designs, which is often mandatory for successful management of the design effort.

For embedded software development, the TLM-based executable specification provides a very fast hardware prototype. Software can begin running on the untimed specification and move to the timed specification, where it can achieve bit-accurate register and memory mappings with realistic hardware performance.

SG73S2BTTD10R5D_Datasheet PDF

From the timed executable specification, the design is refined to an RTL description. This is typically done using hardware description languages like Verilog and, in the future, SystemVerilog. Using co-simulation, each module is verified against its design representation within the context of the whole system. Until all modules are verified, verification progresses, module by module.

This bottom-up RTL verification methodology maintains consistency between the design representations and provides simulation efficiency. Finally, the RTL modules are integrated to perform chip-level tests.

The analog, digital and PLL sections of the CS42528 are designed to minimize the interference from digital switching circuits on sensitive analog components. Critical clock management circuitry provides clock edge control and minimizes switching effects. Separate voltage supply pins and proper attention to the grounding structure and return currents minimize sources of jitter on the output of the PLL. The measured typical clock jitter on the output of the PLL is 150 picoseconds (rms).

The DVD processor uses this clock for audio processing and to maintain synchronization with the incoming rate on the S/PDIF digital interface. Following any required decompression and/or post processing algorithms, the audio data samples are sent to the DACs in the CS42528 for playback. Sample rates from 32kHz up to 192kHz are supported for the S/PDIF interface.

Because the actual S/PDIF receiver, PLL, DACs and clock switching circuitry are integrated into a single part, typical concerns of number of loads, board trace lengths, impedance matching, and transmission line effects of high-speed signals are not relevant. The sources of clock jitter within the system are significantly reduced yielding an audio clock capable of producing high quality audio.

The PLL integrated in the DVD processor synthesizes the audio master clock, which typically runs at 12.288 MHz or 24.576 MHz. The jitter generally found on this clock will cause the DAC's dynamic range to degrade and introduce harmonic distortion.

To minimize the effects of the master clock jitter from a DVD processor, the CS42528 codec has a feature that allows the codec's internal PLL to lock to the incoming sample clock, AUDO_LR, from the DVD processor and generate an internal master audio processing clock to the DACs. Typically, the integrated PLL in the codec is used to extract the imbedded clocking information when receiving data from the S/PDIF receiver.

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