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Like others vendors in the server space, ServerWorks believes that product design will be driven by I/O capability, not processor power. ServerWorks currently sells the four-chip ServerSet III chipset, available in several combinations to suit the emerging segments in the enterprise class. For low- and mid-range applications, a north bridge and south bridge are used; ServerWorks has also designed a three-chip set for the highest-performance OEM products.

EBA40DTAN_Datasheet PDF

Like others vendors in the server space, ServerWorks believes that product design will be driven by I/O capability, not processor power. ServerWorks currently sells the four-chip ServerSet III chipset, available in several combinations to suit the emerging segments in the enterprise class. For low- and mid-range applications, a north bridge and south bridge are used; ServerWorks has also designed a three-chip set for the highest-performance OEM products.

I believe that we are the first company to have created cost effective, embedded flash memory for 0.18-micron CMOS,” said Theo Claasen, chief technology officer for Philips Semiconductors. The ability to embed memory is a vital part of Philips Semiconductors' Nexperia Silicon System Platforms strategy for creating complete products on a single chip.”

The two-transistor cell has stacked gates that Philips said offers many advantages over traditional one-transistor designs. The two-transistor cell makes it easier and faster to test, according to the chip subsidiary of Royal Philips Electronics N.V.

EBA40DTAN_Datasheet PDF

The design also offers cost advantages because the memory size can be precisely tailored to suit the application rather than having to use off-the-shelf memory sizes,” Claasen said. We have developed a two-transistor cell design that has been optimized to provide the benefits of this approach without the drawbacks of increasing the overall size of the memory module when compared to the traditional one-transistor cell.”

Philips said its two-transistor flash memory cell takes up slightly more silicon than a typicalone-transistor cell — 0.78 square microns for the two-transistor cell vs. 0.5 square microns for a typical one-transistor designs. But the overall silicon area for flash functions is reduced because less peripheral circuitry is needed to program and erase the two-transistor cell, according to Philips.

The CMOS18 flash technology uses Fowler-Nordheim tunneling to program and erase the memory cells, which Philips said requires a much smaller charge pump that only delivers microamps. Philips said efficient design of peripheral circuitry for memory control and testing also reduced the overall size of the two-transistor module.

EBA40DTAN_Datasheet PDF

Parallel programming techniques in the embedded flash make testing faster and contribute to potentially lower costs in volume manufacturing. Philips said 16-megabytes of CMOS18 flash memory can be tested in 10-20 seconds vs. 80-140 seconds with typical one-transistor cells. In addition, the two-transistor design overcomes the problem of over-erase at MOSFET threshold voltage variation (Vt) in one-transistor cells because the memory transistor is separated from the selection transistor, according to Philips.

HSINCHU, Taiwan–Silicon foundry giant Taiwan Semiconductor Manufacturing Co. Ltd. here today reported net sales increased 104% to about $790 million (NT$23.6 billion) in the fourth quarter of 1999 from revenues in the 1998 period. TSMC said it shipped a record 551,000 eight-inch equivalent wafers to foundry customers in the fourth quarter, a 90% increase over unit volumes in the previous year.

EBA40DTAN_Datasheet PDF

The strong recovery in silicon foundry demand pushed TSMC's capacity utilization rate to 107% in the fourth quarter last year from just 68% at the end of 1998. The company posted a net income of $280 million (NT$8.3 billion), an increase in profits of 229% compared to $80 million ($2.5 billion) in the fourth quarter of 1998.

TSMC said it is on track to expand its total wafer-processing capacity to 3.4 million eight-inch equivalent wafers in 2000, which would be a 79% increase from the silicon processed in 1999. To do that, TSMC is increasing its capital spending and acquiring Worldwide Semiconductor Manufacturing Corp. (WSMC) as well as taking full ownership of a joint-venture fab from Acer Group (see Jan. 7 story).

The analysis firm also cast doubt on whether UMC's 90-nm chips were really that small, since the M1 pitch is 240 nm and the gate length is 70 nm. The International Technology Roadmap for Semiconductors says it should be 214 nm with 37-nm-long transistor gates. Other notable companies like Intel Corp. and Texas Instruments Inc. also fall short of these metrics, however.

The Chipworks claim kicked up a fuss, with UMC countering that Xilinx had opted not to use low-k intermetal dielectric materials, which are generally more unstable than fluoro-silicate glass. That set UMC on the offensive, trying to draw attention to its advanced research on process technology.

In June, at the VLSI Symposium in Hawaii, the foundry offered details about the substrate engineering techniques it is using to boost performance on 45-nm p-channel transistors by 30 percent or more. In recent IEEE publications, the foundry has also explored ways to enhance silicon-on-insulator (SOI) PMOS transistor performance, which also yields a 30 percent increase in drive current, according to the company.

UMC is studying a method by which it changes the orientation of the substrate crystal so that the holes hit fewer atoms as they move through the gate. It is only being applied to PMOS devices at the 45-nm gate length. The method increases hole mobility by 70 percent, UMC said, which trickles down to a 30 percent drive current increase.

Perhaps the most clever of the UMC projects in the lab, however, is one regarding partially depleted SOI. The foundry is using what is typically deemed a disadvantage-the quantum-mechanical tunneling effect-to increase drive current in PMOS transistors.

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