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In the interim, Hynix has been left in a state of turmoil as chief executive C.S. Park resigned in protest over Tuesday's board of directors' vote.

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In the interim, Hynix has been left in a state of turmoil as chief executive C.S. Park resigned in protest over Tuesday's board of directors' vote.

He says that a number of issues need to be addressed, including that of design registration. This is where a component manufacturer recognises a distributor's design contribution, but sometimes only certain components qualify.

This raises issues when the distributor's design work is more for a module than a single piece.

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There are also different policies over reward structures which can vary between options such as one-off fees, a commission and something akin to a royalty.

Patrick Zammit, president of EBV Elektronik, set out some of his thoughts on new reward systems”. EBV is part of Avnet's worldwide empire.

Core distribution will, in his view, remain a margin-based business.

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But areas such as supply chain and design and engineering may move to a combination of margin and service fees, consulting could become a service fee-only discipline and the design represen-tative function will attract commissions.

Under the current system, Zammit estimates that design accounts for 50% of a distributor's profit margin, with traditional fulfillment and logistics work accounting for the rest.

tvs diode selection

Accellera is working on two related initiatives for assertion language standards. One will select a formal property language, while the other will add an assertion construct to Verilog, probably based on the Superlog Design Assertion Subset. This will be included in this year's System Verilog release.

A given protocol might be as complex as fifteen different layers of embedded logic. No hardware-based logic analyzer could ever show the results in the form of 64 or 128 uni-dimensional lines.

Thus, the ability to convert an RFC into a textual format has a double benefit: It uses the specification to not only generate the protocol stack and it simultaneously generates the information necessary to drive a protocol analyzer's decode engine. Not only are you testing the stack – you are also running it over a communications link, and you are able to monitor that link with the same data you used to design the stack. This goes far beyond what you can expect to accomplish with general-purpose tools and methodologies.

Axel Tillmann is chairman and CEO of EDA startup Novilit, Inc.

GENEVA–STMicroelectronics today rolled out a new 4-megabit flash memory designed specifically to support digital signal processors from Analog Devices Inc. with on-chip programmable logic.

The integrated programmable logic device (PLD) block provides 3,000 gates and 16 macrocells on the 4-Mbit flash memory. The DSM2150F5 also has up to 40 multifunction I/O pins and two independent flash memory arrays of 512 kilobytes and 32 Kbytes of storage, said the European chip maker.

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