TAIPEI – AU Optronics Corp. will show a 15.6-inch glasses-free 3-D display here next week at Display Taiwan . The component is one of a handful to be shown at the event demonstrating the island nation's progress in various optical technologies.

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TAIPEI – AU Optronics Corp. will show a 15.6-inch glasses-free 3-D display here next week at Display Taiwan . The component is one of a handful to be shown at the event demonstrating the island nation's progress in various optical technologies.

ADR827ARMZ-REEL7_Datasheet PDF

TAIPEI – AU Optronics Corp. will show a 15.6-inch glasses-free 3-D display here next week at Display Taiwan . The component is one of a handful to be shown at the event demonstrating the island nation's progress in various optical technologies.

We think we can eke out one more turn of the crank out of copper, so we are not looking at optics yet,” said Ramin Neshanti, chairman of the PCI SIG's serial communications working chair.

It took the PCI SIG about four years to hammer out its 8 GT/s PCIe Gen 3 spec which required new signal encoding and equalization schemes. The Gen 4 spec should take a similar period, but this time the focus will be less on silicon and more on the board-level channels through which signals pass, Neshanti said.

ADR827ARMZ-REEL7_Datasheet PDF

Specifically, Gen 4 will probably be limited to distances of about eight to 12 inches compared to 20 inches for Gen 3. Engineers wanting longer reaches will need to use repeaters, a potential growth area for PCIe silicon.

The Gen 4 boards may need to use new materials, via designs and backwards-compatible connectors designed for improved signal integrity to reduce impedance discontinuities. We think we have achieved about as much as we can scaling silicon,” said Neshanti who also serves as an I/O standards manager at Intel.

That's a big shift for the PCIe community which has not previously required major changes of board makers. Typically the PCI SIG has thrown its hardest problems to chip makers such as AMD, Intel, NEC and others to ease problems for its less technically sophisticated supply chain among high volume PC board and system makers.

ADR827ARMZ-REEL7_Datasheet PDF

Nevertheless, some significant silicon shifts are ahead. Transceivers for Gen 3 were the first to use techniques to massage signals, adopting single-tap decision feedback equalization (DFE).

Gen 4 transceivers will need to use multi-tap DFE. How many taps they will need is not yet clear.

ADR827ARMZ-REEL7_Datasheet PDF

There also will be heavy investments needed from test equipment vendors to do some very creative probing solutions either on chip or somehow as an add-in,” said Neshanti. Agilent, LeCroy and Tektronix are among the testers involved in the work, but we don’t know which will step up first,” he said.

Work has so far focused on electric and analog aspects of the physical-layer design for PCIe Gen 4. Over time, exploration will start on logical-layer and protocol improvements in areas such as latency reduction, forward error correction, deeper pipelining and error reporting and control.

Demonstration rooms and table tops will be available for companies wishing to exhibit at the conference, with a reduced charge available for AES Sustaining Members.

More information and registration here .

This article originally appeared on EE Times Europe.

Xilinx will showcase its optical transport network (OTN) portfolio and will discuss how it provides multiple solutions that can help users overcome high bandwidth optical transport network (OTN) challenges at the Linley Tech Carrier Conference at the DoubleTree Hotel in San Jose from June 7 – 8, 2011.

During the conference, Xilinx Solution Architect, Communications Business Unit, Shreyas Shah, will explain how FPGAs are addressing increasing bandwidth demands in carrier/optical networking. Shah's presentation will also cover quality of service (QoS) and traffic management requirements for high bandwidth networks.

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