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Its detractors argue that the Oxford study's sample is too small to be meaningful. In blogs and Internet forums, the research conclusions have been called everything from shoddy scholarship to shameful bigotry. One engineer commented that the study showed once again that sociology is a useless pursuit.

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Its detractors argue that the Oxford study's sample is too small to be meaningful. In blogs and Internet forums, the research conclusions have been called everything from shoddy scholarship to shameful bigotry. One engineer commented that the study showed once again that sociology is a useless pursuit.

Competitors such as Juniper Networks and Redback Networks–and Cisco's existing 7600 series routers–typically slot multiple cards in a chassis or stack appliances in a rack to handle all the features increasingly being processed on the network edge, said Eve Griliches, a telecom analyst at International Data Corp.

The more integrated you get it, the better performance you get when you are trying to run all the services at once–and eventually users will want to run all these services at once,” Griliches said.

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Key to the system is the 1.3-billion-transistor flow processor, an 80-watt chip made in a 90-nanometer process at Texas Instruments and designed using Cisco's customer-owned tooling. Each of its 40 Tensilica cores can handle up to four threads, far beyond the raw thread-level parallelism of Sun's 65-nm Niagara or Intel's 45-nm Penryn server CPUs.

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We looked outside and internally to see if there was anything we could use, but nothing came close,” said Nikhil Jayaram, director of engineering in Cisco's midrange routing group. Other architectures were about packet processing, but we wanted to do flow processing of stateful traffic.”

Multicore processors and complex aggregation routers are converging in a way that means the most-complex communication processing chips now dwell at the edge of the public network,” said Loring Wirbel, director of the EE Times Market Intelligence Unit. The center of the network now means big, dumb, high-speed bit pushing, while all the smarts reside at the edge of the public network, and core routers like Cisco's CRS-1 are no longer the premier platforms for high-performance network processors.”

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The company hopes the processor will be used in a wide range of routers and be actively upgraded for years in the field. But success in the dynamic edge-networking market, which is growing at double-digit rates, is not assured, said Griliches of IDC.

The market is littered with router makers who have tried to deliver all the services in one box, but have not done so sufficiently well, because it is not easy to do. Putting everything in one chip is a step in the right direction. A lot of their competitors will be moving in this direction,” she said.

And some ASIC technologies are doing better than others in the market. For years, the ASIC business was split into two big markets: standard cell and gate array. For standard-cell parts, an OEM would go to an ASIC house and use its design tools to devise a chip nearly from scratch. In contrast, gate arrays are predefined, unconnected parts that are held in stock prior to metallization.

More recently, vendors have rolled out so-called structured ASICs, which claim the advantages of both cell-based designs and gate arrays. Structured ASICs have predefined metal layers, but designers can precharacterize what is on the silicon.

There has been more hype than sales in structured ASICs. At one time, some predicted that the structured ASIC market would hit $1 billion by 2007 or 2008. Today, structured ASICs are a modest $150 million business, according to iSuppli.

As a whole, the structured ASIC business has been a bust,” according to Selburn. LSI, NEC and others have exited that market. The remaining players in structured ASICs are Altera, AMI, ChipX, eASIC and a few others.

Some vendors are moving full speed ahead in the arena. One vendor, ChipX, has recently introduced a new class of devices that they refer to as a Hybrid ASIC, which involves the implementation of a structured ASIC as IP on a standard cell device.

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