WK73R1JTTD4322F_Datasheet PDF

– 20% responded that they used XRF testing, either using their own XRF scanning equipment, or by outsourcing the scans

– 80% responded they required lab tests or certifications of compliance.

WK73R1JTTD4322F_Datasheet PDF

– 2.5% responded that they required factory audits– 2.5% of respondents indicated they had their own in-house chemical analysis capabilities to test for compliance

(The responses exceeded 100% because some respondents indicated more than one validation approach.)

How does your company manage compliance data?

WK73R1JTTD4322F_Datasheet PDF

– 5% using software tool

– 30% file the hardcopies of the compliance data.

WK73R1JTTD4322F_Datasheet PDF

– 35% using spreadsheet

– 17.5% using combination of spreadsheet and manual filing

In fact, at one point in the qualification, our test lab, following the JEDEC specification to the letter, submerged the DUT board in liquid flux. The chlorine based flux system caused a drift in the humidity output, but did not cause a failure of the sensing die. After this mistake,” we only allowed deionized (DI) water to be used to clean the part. The sensor die is not damaged by DI water and short exposure to hazardous chemicals will not damage the sensor (perhaps only shifting the reading).

These types of humidity sensors are known to shift less than 1% RH in reading when exposed to isopropyl alcohol, hydrogen peroxide, and sodium hypochlorite. Longer term or high concentration exposure to chemicals like ammonia hydroxide, and acetone may cause a failure of the sensor. It is recommended that the design engineer carefully assess the potential for chemical exposure before finalizing the design using the ChipCap.

Another critical test for reliability for the ChipCap is the high-temperature operating-life and early-life failure rate tests. These tests were run at 85C for 1,000 hours and at 85C for 160 hours, respectively. Results of this testing indicate a calculated mean time between failure (MTBF) of 3.6 operating million hours.

Additionally, electrical overstress (EOS) tests selected were ESD Human Body Model (HBM), Charged Device Model (CDM), and Latch-Up. The test for HBM was ±2 kV per pin and for CDM, it was ±500V all pins and ±750V for all corner pins. Despite the size of the IC package (thicker SO-14) the device passes the ESD CDM test easily. Perhaps the open cavity” design, with less bulk plastic reduces the package charge buildup.

The Latch-up test is performed with injection of ±100 mA into each pin. The key for this test is that one must run the device at its maximum operating temperature to ensure the highest probability of activating any latent latching silicon control rectifier (SCR) structures in the silicon and substrate regions. This is another key test for design validation to ensure that destructive latching or stuck-at-faults do not occur for our customer's application.


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