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The STB has been developed by Sumitomo Electric Networks, Inc., a major Japanese equipment producer for home entertainment and broadband service providers, with operations around the world.

MIKQ9-19PH048_Datasheet PDF

The STB has been developed by Sumitomo Electric Networks, Inc., a major Japanese equipment producer for home entertainment and broadband service providers, with operations around the world.

Networking is a vital part of maintaining and growing a career. But networking events often involve dry appetizers, bland conversation, and white wine (maybe we should say whine”?). Not so at DESIGN West.

Find the Expo Floor Tech Lounge and you’ll find free beer and snacks like bacon (yes, bacon), plus a great opportunity to network with your peers, exhibitors, and industry luminaries.

MIKQ9-19PH048_Datasheet PDF

Look to the Tech Lounge throughout the event for such networking opportunities as well as other opportunities.

DESIGN West ,  April 22-25, in San Jose, is hosted by UBM Tech.  Register here.

MIKQ9-19PH048_Datasheet PDF

You’ve heard of Arduino, but are you up to speed on it?

SparkFun, which can’t help but make everything it touches fun, will be running 45-minute speed training sessions on Arduino at DESIGN West. See what SparkFun’s Lindsey Craig has to say about the short sessions here and get the details here.

MIKQ9-19PH048_Datasheet PDF

But Arduino is just the tip of the open-source iceberg. There’s more open source in the world of engineering than ever before and we’re helping keep you on top of it all in these community-focused, peers sharing knowledge with peers, sessions and tracks.

Stop in on the Open-Source Hardware Discussion panel, follow the Linux track, and get your Android certificate at the show.

Stop! Did you note the fact that the on-chip dual ARM Cortex-A9 processor subsystem in the SoC devices will be running at 1.5GHz ? And this is in the so-called midrange devices, which is why I'm eager to hear more about the processor subsystem in the Stratix 10 SoC devices as discussed above. All of which leads us nicely to the following graphic:

Although simple, to me the above graphic is one of the most startling I remember. When an FPGA vendor announces a new generation of devices, the new midrange devices will obviously trump” the previous generation of midrange devices, but their performance cannot be so high as to encroach into the realm of the high-end devices implemented at the same technology node.

So, the fact that Altera is implementing its next-generation high-end devices using a different technology node (Intel’s 14nm Tri-Gate process), which provides such a large performance boost, means that Altera feels free to make its next-generation midrange devices out-perform its current generation high-end devices (if you see what I mean).

The key takeaway from the above graphic is that Arria 10 midrange devices will consume 40% less power than their Arria V predecessors while offering 15% greater performance than the current Stratix V high-end devices. My mind is truly boggled!  Development suite delivers breakthrough productivity to Generation 10 Generation 10 devices are supported by Altera’s Quartus II development software and tools for higher level design flows that include a software development kit for OpenCL, a SoC Embedded Design Suite and DSP Builder tool.

This leading-edge development tool suite enables design teams to maximize productivity while making it easier for new design teams to adopt Generation 10 FPGAs and SoCs in their next-generation systems. The Quartus II software will continue to deliver the industry’s fastest compile times by providing Generation 10 FPGAs and SoCs an 8X improvement in compile times versus the previous generation. The substantial reduction in compile times is the result of leading-edge software algorithms that take advantage of modern multi-core computing technologies.


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