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This ensures that the qualities required for the job are properly identified in screening and selection and that training is aligned with the work environment and learning style of the class,” she says. When this process is in place, managers get the people they need to get the job done.”

SG73S2ETTD1070F_Datasheet PDF

This ensures that the qualities required for the job are properly identified in screening and selection and that training is aligned with the work environment and learning style of the class,” she says. When this process is in place, managers get the people they need to get the job done.”

The verification environment also employs pseudo-random program generators to further enhance verification testing. These random program generators create tests that trigger complex interactions across different parts of the processor. The present implementation of the environment employs two configurable pseudo-random diagnostic generators.

One of the pseudo-random diagnostic generators is written in object-oriented Perl and the second generator is based on Synopsys' Vera Stream Generator, which is provided with the Vera HVL. Both generators employ instruction-list templates that are combined in random sequences to create complex diagnostic programs.

SG73S2ETTD1070F_Datasheet PDF

A major issue with verifying complex logic designs like microprocessors is ensuring that the diagnostic programs test the entire design. This issue is especially bothersome with randomly generated diagnostic programs that may inadvertently check one part of a design repeatedly while overlooking the rest. Tensilica addressed this problem with a functional coverage methodology based on Forte Design Systems' Perspective results-analysis tool. The results of this analysis help to steer the diagnostic generators in new directions to increase the overall verification test coverage.

At the same time, Vera-based monitors (which help to verify the correct implementation of micro-architectural features) and 0-In Design Automation's assertion-based signal and bus monitors check the processor's internal RTL state. In addition, VCS Coverage Metrics, an HDL-code-coverage utility included with Synopsys' VCS Verilog simulator, checks the verification coverage of the processor's RTL code while FSM (finite state machine) monitors, also written in Vera, check coverage of state machine operations within the processor by checking each FSM's state and the state transitions triggered by the diagnostic programs. Finally, additional checking is performed by lint tools, Design Compiler synthesis checking, and formal verification using Conformal LEC from Verplex.

The diagnostic checking programs and monitors and the RTL and ISS simulation models run simultaneously within a co-simulation environment. The Vera-based co-simulation environment compares architecturally visible states in the RTL and ISS simulations. Tensilica selected Vera as the test bench tool because it works well with multiple HDLs and simulators. This verification methodology has allowed Tensilica to verify a very large number of Xtensa processor configurations using myriad versions of the verification programs and trillions of simulation cycles, over many months and all in an efficient and automated fashion.

SG73S2ETTD1070F_Datasheet PDF

Help for designers

Because SoC designers can add instructions to the Xtensa microprocessor, Tensilica's verification methodology must provide a way for designers to verify the added instructions. Tensilica provides three sets of tools to help designers verify their custom instructions: a framework that automatically generates AVPs using customer-provided test vectors, automatically generated MVPs that verify the operation of both the core and the designer's ISA-extension logic, and Verplex scripts for formal verification of extension semantics against instruction references.

SG73S2ETTD1070F_Datasheet PDF

It's not sufficient to verify a processor's operation in the absence of other system components (such as memories and bus interfaces) because a processor is never employed in an SoC without these other components. Consequently, a configured system verification test bench (Figure 2) is also part of this verification methodology. The test bench comprises modules for memory caches, local-memory RAMs and ROMs, a JTAG controller, and a bus interface that connects the processor core to other modeled system resources.

Ancillary modules in the test bench include interrupt, bus-error, and random interface stall generators; peripheral models; and a system memory model. Except for the processor models, all of the Xtensa test bench modules are behavioral models implemented in RTL, C, or Vera depending on the abstraction level required. Tensilica also provides a model test bench for post-synthesis, gate-level simulation. This gate-level test bench is used for sanity checking of the synthesized logic and for power estimation.

SWINDON, England — Intel Corp. has joined leading communications component and equipment companies in forming a non-profit corporation, called WiMAX, to help promote and certify the compatibility and interoperability of broadband wireless access equipment.

The group's efforts will help accelerate the introduction of IEEE* 802.16.a wireless broadband equipment into the marketplace, speeding up last-mile broadband deployment worldwide.

WiMAX members include Airspan, Alvarion, Aperto Networks, Ensemble Communications, Fujitsu, Hughes Network Systems, OFDM Forum, Nokia, Proxim and Wi-LAN, Intel said.

The 802.16a standard, approved in January of this year, is a wireless metropolitan area network technology that will connect 802.11 hot spots to the Internet and provide a wireless extension to cable and DSL for last mile broadband access. It provides up to 50-kilometers of range and allows users to get broadband connectivity without needing a direct line of sight with the base station. The wireless broadband technology also provides shared data rates up to 70-Mbit/s,


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