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Jurvetson agreed creating good models would be the biggest challenge, except for data rich companies like Google and Apple. Sarah Tavel of Benchmark also questioned the use cases and if the overhead required for what would typically be relatively low-powered devices would create enough value for effort.

42-01008_Datasheet PDF

Jurvetson agreed creating good models would be the biggest challenge, except for data rich companies like Google and Apple. Sarah Tavel of Benchmark also questioned the use cases and if the overhead required for what would typically be relatively low-powered devices would create enough value for effort.

Once the ATE PCB thermal profile is perfect, it’s then set up on the reflow oven to run the live product. The board may go through reflow two times in case some of its components need rework.

Stencil Design A proper stencil is used to precisely dispense solder paste onto components on an ATE board. At first glance, inexperienced ATE PCB assembly companies may view such a stencil design as merely another simple step in the assembly process with little or no extra effort put into it. It’s just the opposite. Correct, precise stencil design is the linchpin of an ATE board assembly, and thus is extremely important.

42-01008_Datasheet PDF

Let’s take a small radio frequency (RF) surface mount (SMT) component. Stencil apertures must be accurately designed so that the stencil can accommodate the component. Knowing and understanding stencil aperture patterns and how they affect solder reflow behavior are especially important; however, they are often ignored. When that, and other, factors occur, considerable rework is the result. In short, omitting key steps in an ATE board stencil design defeats the whole purpose of placing an ATE board on an automated assembly.

The assembly process can incur adverse effects when the stencil is not accurately designed. There can be such flaws as a number of tombstones and bridging when an incorrect stencil is run through the pick-and-place and reflow process. Fig. 4. shows an example of tombstoning. Tombstones refer to components that are lifted on one side.

42-01008_Datasheet PDF

This flaw could be due to inaccurate stencil design, among other factors. This results in costly and time-consuming amounts of touch-up and re-work after the assembly is completed. For the ATE PCB customer, this extra work translates into delayed delivery shipment, cost increases, and considerable (but unnecessary) stress being placed on the board’s existing components. Designing and implementing the right stencil can eliminate all these extra problematic areas.

Avoid DUT Compromises The device-under-test (DUT) site (or sites) is the most critical part of an ATE PCB. This is where a component or chip is placed for testing. There can be one or more DUTs on a board; e.g., the four DUTs shown in Fig. 5. Others can be a dual-site board with two DUTs where a microprocessor (µP) or central processing unit (CPU) is to be placed for testing.

42-01008_Datasheet PDF

If the DUT is compromised in any way, the ATE PCB becomes useless. Hence, details are of the utmost importance. For example, nut fasteners, referred to as PEM nuts (brand name Penn Engineering & Manufacturing Corp.) are used to keep the DUT socket in place. If these are not properly installed, the DUT socket is not correctly attached. As a result, the chip or component to be tested cannot be loaded onto, or tested on, the DUT.

The wireless modem provides the broadband interfaces to the subscriber. Figure 2 illustrates an expanded block diagram of the wireless modem.

The wireless modem contains RF and intermediate frequency (IF) transceivers that translate the data between RF and baseband. The modem's baseband processor performs all theVOFDM PHY and DOCSIS MAC layer processing (see Figure 3 ). The host processor runs the wireless modem software and provides USB and Ethernet interfaces. Other modules can be incorporated to provide voice interfaces or interfaces to other networks such as home phoneline networks (HomePNA) or wireless LANs (WLANs) (802.11).

Inside VOFDM

The VOFDM signal structure breaks a broadband signal into a large number of narrowband tones (see Figure 4 ). The VOFDM signal structure contains data tones, zero tones, and training tones. Data tones carry the information bits, zero tones are necessary for channel spectral mask compliance, and training tones are used by the receiver forsynchronisation and channel estimation.

Training tones are transmitted with known relative amplitude and phase and are used by the receiver to form an estimate of the channel. This channel estimate is used to mitigate theeffect of multipath (see Figure 5 ). The channel estimation process also produces an estimate of the SNR present on each tone. This information is used later during the decoding process. Since the channel estimate is updated dynamically, the system operates robustly in the presence of time varying multipath.

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