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When combined with the Microblaze microprocessor, the so-called 'Quixilica' co-processor produces a sustained performance of 50-MFLOPS (million floating point operations per second) and peak performance of up to 100-MFLOPS on the XC2V1000-4 at 100-MHz clock frequency, the company estimates.

32324238-001-08_Datasheet PDF

When combined with the Microblaze microprocessor, the so-called 'Quixilica' co-processor produces a sustained performance of 50-MFLOPS (million floating point operations per second) and peak performance of up to 100-MFLOPS on the XC2V1000-4 at 100-MHz clock frequency, the company estimates.

With imprint lithography you can make the patterns as small as you want,” Chou said. CD critical-dimension control is automatically better than photolithography. But we have to solve the alignment issue by pressing the mold without rotation.” Nanonex claims to be a turnkey supplier that teaches customers how to create the templates using a converted scanning electron microscope developed at Princeton.

Low-pressure system

32324238-001-08_Datasheet PDF

The competitive juices are flowing at suppliers and research labs, as engineers figure out ways to optimize the key steps in imprint lithography. MII's chief technical officer, S.V. Sreenivasan, a mechanical-engineering professor on a two-year sabbatical from U.T.-Austin, said he and MII co-founder Grant Willson, a polymer chemist at UT-Austin who developed photoresists during a long career at IBM Corp., have devised a room-temperature, low-pressure imprint system that does not require the high temperatures used in earlier imprint systems.

And MII has developed an inkjet-like microdispenser that applies the monomer liquid on the area just prior to the lowering of the template. The imprint-and-step function takes about 20 to 30 seconds per field, improving throughput.

The company is applying for patents on its method of stopping the flow of the monomer just at the edge of the area to be patterned, Sreenivasan said. He declined to describe the method until the patents are filed.

32324238-001-08_Datasheet PDF

Schumaker, a former Bell Labs researcher who has worked at several equipment companies, said MII is not trying to be all things to all people. Initially we will go after MEMS microelectromechanical systems, biodevices, the thin-film heads used in hard-disk drives, packaging and the 3-D-type patterns with four or five levels, like the stair-stepping structures used in optical devices.”

Boosting throughput

32324238-001-08_Datasheet PDF

Many photonic devices are created using direct-write electron-beam machines, which can take up to an entire day to pattern one wafer. Imprint lithography is a means of enhancing the throughput of e-beam, Schumaker said, by using the time on the e-beam machine to scribe the pattern on a template. The template can be used in an imprint machine like MII's Imprio, which can process several wafers per hour.

Sreenivasan said he believes that more fully integrating the dispense and imprint steps will boost throughput to about 30 wafers/hour, from five or six now. And as more-precise mechanical components are developed — including the leveling flexure” subsystem to position the template — alignment can be improved to chip industry standards.

Take a typical circuit block of 200 transistors. The fun part is creating and selecting the right topology for your design — figuring out where to place your transistors and what connections to make. The tedious part is sizing that design — going through exhaustive simulation, changing device sizes, keeping track of all of the performance tradeoffs, making sure the design is robust to all manufacturing and environmental process corners. Interestingly, this transistor-level tedium has extended beyond just analog designs to mixed-signal and custom digital IC designs as well.

Tools have recently come to the market to automate this tedium. Underlying these tools are algorithms able to handle continuous and discrete transistor variables simultaneously, handle 200+ transistors, handle 30+ specifications, and consider several design corners simultaneously. These tools can even work in the designer's trusted tools environment, using his or her design entry environment to input schematics and a trusted simulator to validate designs. Automating the tedium, though, must not cause designers to lose control.

With any design there are constraints and objectives. Constraints are those specifications that must be met (phase margin must be greater than 60 degrees, for example) and objectives are those specifications that should be maximized or minimized (such as power or area). With objectives come tradeoffs — one can compromise a little area for better power, or compromise some phase margin for gain.

Tools cannot and should not make these objective tradeoff decisions for the designer. Rather, tools should allow designers to generate and analyze as many optimal designs as possible, present what the performance possibilities and tradeoffs are, and provide an easy method for the designers to choose the most appropriate design for their application. The chosen design becomes part of the integrated circuit; those not chosen for the particular application under consideration are still captured and become part of the intellectual property library of the company, stored as pre-validated designs for future use.

With automated transistor sizing tools such as these, the tedium is eliminated and the designer is left in control. Computers automatically perform the exhaustive simulation to size transistors and produce more robust designs, and designers can focus on topology design and design selection.


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