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iSuppli views Spansion's announcement as a landmark event because for the first time, a memory supplier is providing value-based solutions for mobile phones that go beyond the traditional goal of delivering more memory bits at a lower cost. Throughout the history of the mobile-phone memory business, the focus has been squarely on providing the highest density at the lowest cost. However, with growth in the NOR market having slowed over the past few years, Spansion is seeking new approaches to drum up revenue.

ERJ-P06F6493V_Datasheet PDF

iSuppli views Spansion's announcement as a landmark event because for the first time, a memory supplier is providing value-based solutions for mobile phones that go beyond the traditional goal of delivering more memory bits at a lower cost. Throughout the history of the mobile-phone memory business, the focus has been squarely on providing the highest density at the lowest cost. However, with growth in the NOR market having slowed over the past few years, Spansion is seeking new approaches to drum up revenue.

In developing complex devices such as microprocessors, designers work concurrently on block refinement in a design hierarchy, using constraint-aware tools to ensure that each block design can proceed in parallel. Here, logic designers add constraints, confident that layout engineers will incorporate their design intent in physical layouts.

In this approach, however, logic designers do not need to wait for layout engineers to gain an early understanding of the manufacturability of their designs. With this new approach, designers can allow the tool to complete a constraint-driven physical design, driving the tool with only critical constraints representing the most important issues of concern to the logic designer.

ERJ-P06F6493V_Datasheet PDF

Later, the addition of more detailed constraints assists layout engineers in achieving a design that is optimized across both design and manufacturing constraints. At the same time, detailed 3D-space-based models account for all neighboring structures within a prescribed halo” of the structure of net of concern — providing the accuracy needed for reliable prediction of silicon performance (Figure 2).

Whether the layout designer works interactively with the design tool or allowing the tool to complete the design automatically, each shape is correctly routed according to those rules and constraints. With this approach, a physical design solution is implicitly correct by construction,” because each physical design decision occurs in the context of the constraints and design rules associated with each structure. Nevertheless, designers can override these guidelines when their experience tells them such a violation is needed to meet design or manufacturing objectives.

ERJ-P06F6493V_Datasheet PDF

Fundamental change

Already applied to 65nm tapeouts to date, this new constraint-driven design methodology has provided the flexibility needed to tune physical designs based on performance or specialized structures (Figure 3). This capability is critical in optimizing designs in advanced processes with multiple metal layers dedicated to high-speed interconnect. Critical nets can be marked as such by logic designers for automatic routing on layers intended specifically for high-performance interconnect — eliminating manual pre-routing tasks that in the past typically required months to complete for complex microprocessor designs.

ERJ-P06F6493V_Datasheet PDF

More accurate modeling is also needed for faster convergence. By having a router and checking system correlated with the sign-off physical verification system, the routing is correct-by-construction with no surprises nor long repair iterations.

When ordering, you specify the center frequency and bandwidth in which your input signal will fall in order to establish a desired sampling frequency.

For more details contact Optichron, Inc., 4221 Technology Dr., Fremont, Calif. 94538. Phone: 510-249-5230. E-mail: sales@optichron.com

Optichron , 510-249-5230, www.optichron.com

Plan-Les-Ouates/Geneva, Switzerland – STMicroelectronics has announced a new generation of its serial Flash memory chips, with densities from 1 to 4 Mbit, which are intended specifically for demanding automotive applications with high reliability requirements. The M25P10-A, M25P20 and M25P40 memories – 1 Mbit, 2 Mbit and 4 Mbit, respectively – are thought to be the first serial Flash devices tough enough to be specified and made available for the automotive environment. They are produced using ST’s volume-proven state-of-the-art technology to offer reliable solutions for automotive applications. The products are Automotive Grade certified, and are qualified to the AEC-Q100 standard. In addition, the devices are tested through ST’s proprietary High Reliability Certified Flow (HRCF) procedure to guarantee operation over the full -40 °C to +125 °C automotive temperature range, and to meet automotive quality and reliability demands. This testing flow is combined with statistical tools such as SBL (Statistical Bin Limit) and PAT (Part Average Testing) to screen out early failures and outliers (on wafer and die), with the aim of meeting the automotive Zero-ppm target – total reliability.

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