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Philippe Hurat, Marketingchef beim Startup-Unternehmen Clear Shape Technologies, hält die Problemsuche auf Maskenebene zwar für sinnvoll; noch besser sei es aber, die Probleme bereits zu einem früheren Zeitpunkt zu vermeiden. Hurats Präsentation bot eine kurze Vorschau auf Clear Shapes Technologie. Diese basiert auf einem kompakten Silizium-Integritäts-Fertigungsmodell” statt auf Design-Rules.

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Philippe Hurat, Marketingchef beim Startup-Unternehmen Clear Shape Technologies, hält die Problemsuche auf Maskenebene zwar für sinnvoll; noch besser sei es aber, die Probleme bereits zu einem früheren Zeitpunkt zu vermeiden. Hurats Präsentation bot eine kurze Vorschau auf Clear Shapes Technologie. Diese basiert auf einem kompakten Silizium-Integritäts-Fertigungsmodell” statt auf Design-Rules.

Delivering a keynote address at Denali's Memcon event here Wednesday (Oct. 12), Gogolewski said design costs are skyrocketing, mostly due to increased time and effort spent on architecture and verification. Another challenge is securing intellectual property and making it interoperable, something that is straining the relationship between the EDA community and the semiconductor industry.

Putting more engineers on the project does not necessarily solve the problem,” said Gogolewski, who noted that IP blocks are still painstakingly stitched together, largely through brute force.”

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Citing data compiled by Philips Semiconductors, Gogolewski said the software content of system-on-chips (SoCs) is growing 10-fold every six years. Design starts are trending downward, he said, because design costs are rising. He said a new chip design requires a $100 million market opportunity, something he noted is rare.

According to some metrics, Gogolewski said, software development costs have surpassed hardware development costs.

We often hear that verification is 70 percent of the total design effort, but not about the other 100 percent going into software,” Gogolewski said.

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Part of the problem, Gogolewski said, is that the industry is expending so much energy fitting together IP blocks and then verifying interoperability. For example, he said, there is no guarantee that one PCI bus core can be swapped out for another.

As an industry, we cannot let this continue,” he said.

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Gogolewski called for closer industry collaboration around bus and interface standards. He pointed to PCI Express as a shining example, noting that Intel Corp.'s early embrace of the spec pushed much of the industry to support and develop it.

Too often, Gogolewski said, standards efforts result in a piece of paper” describing the agreed upon components of a standard. That's far from a complete, workable standard, he added.

SAN JOSE, Calif. &#151 Integra Technologies LLC, once part of Amkor Technology Inc., on Monday (Oct. 10) announced the commencement of its operations in the chip-testing sector.

The management team of Integra recently completed a management buyout of Amkor’s chip-testing operations in Wichita, Kan. and Santa Clara, Calif.

Integra (Wichita) will focus on semiconductor testing for commercial, military, and avionics applications. Integra is a full service semiconductor test supplier providing a complete range of engineering development, production, characterization, qualification, environmental conditioning, ESD, and latch-upservices.

Our core testing operation in Wichita, Kansas has been in business since 1983,” said Becky Craft, president of Integra Technologies, in a statement. Our ESD testing operation in Santa Clara, California has been operating for over 15 years. This extensive experience base, and our broad range of test services, will enable us to continue to provide test services to any company involved with semiconductor design, development, evaluation and production.”

AccelChip added three new AccelWare Intellectual Property generators to its AccelWare Advanced Math Toolkit. The generators can be used in the deployment of adaptive signal processing filter algorithms commonly found in wireless solutions such as smart antenna beamforming applications and MIMO-OFDM wireless LAN design.

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