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In Figure 13 , clocks C1 and C2 have time periods 10ns and 7ns respectively. Notice, that the minimum phase difference between the two clocks is 0.5ns, which is very small. So, there are chances of metastability and a synchronizer would be required.

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In Figure 13 , clocks C1 and C2 have time periods 10ns and 7ns respectively. Notice, that the minimum phase difference between the two clocks is 0.5ns, which is very small. So, there are chances of metastability and a synchronizer would be required.

The next installment of this series can be found at Comprehensive UWB product testing: Part 3.

About the authors Fanny Mlinarsky is the President of octoScope, a consulting firm focusing on architecture and performance of wireless data communications systems. She can be reached at .John Ziegler is a data communications software development consultant with experience in communications protocols including 802.11, SIP, and a variety of voice and video technologies. He can be reached at .

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Acknowledgements:

We would like to thank Agilent, ETS-Lindgren and Ixia for providing the equipment for our test. Agilent has provided the E4440A PSA Series Spectrum Analyzer and ETS Lindgren has provided Model 3117 Double-Ridged Waveguide Horn antenna for UWB spectrum measurements. Both the analyzer and the antenna cover the entire UWB frequency band from 3.1 to 10.6 GHz. Ixia has provided IxChariot for IP layer throughput measurements.

Over the past decade, designers around the world have argued over the relative merits of using ASICs or FPGAs to implement digital electronic designs. This ongoing discussion has typically positioned the performance advantages and low power consumption of fully customized ICs against the flexibility and low NRE costs of FPGAs. Should a design team make the formidable up-front NRE investment in an ASIC design in order to maximize performance, reduce footprint and drive down costs at high volumes? Or is the design team building an end product for a market that demands the highly configurable feature sets and quick turnaround that only FPGAs can provide?

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Surprisingly, the escalating challenges of high-density IC design are, in many ways, making that argument irrelevant. As ASIC designers migrate to each new process node, designs grow more complex, software content increases and verification runtimes lengthen. Moreover, recent research indicates that over 60 percent of respun ASICs fail not because of issues with timing or power, but because of logical or functional errors. For this reason, functional verification has become the single most critical phase of the ASIC development cycle, and often the most time-consuming. An increasing number of ASIC designers find that they can best meet their requirements by prototyping the functional equivalents of their designs as FPGAs. In fact, more than 90 percent of all ASICs today are either partially or completely prototyped as FPGAs before tape-out. Thus the question is no longer whether to implement an IC design as an ASIC, or as an FPGA. To meet the demands of today's markets, most design teams must do both.

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Verification options

Given the critical need for first-pass silicon and the escalating possibilities for bugs as ASIC densities climb and design complexities increase, designers clearly need a verification methodology that can not only find all bugs in complex chip designs but also do so in reasonably short times. Traditional software simulation techniques can no longer support design teams who are racing to squeeze into tight time-to-market windows. Take a typical mobile phone chipset design. Although RTL simulation offers a high level of visibility into the design, the low performance associated with software simulation means that booting the phone chipset could take as long as 30 days, making it unfeasible and, therefore, significantly limiting the level, and amount, of verification possible. Hardware/software co-simulation approaches that use higher-level models can reduce the time required for this sort of OS boot to 10 days, but even that is still not very useful. Moreover, these approaches still require the development of complex testbenches, which, by their very nature, are always incomplete. A C” model simulation offers shorter runtimes, perhaps even of only 24 hours, but it can't deliver the level of detail typically required by ASIC designers.

Number 10 is a feature on achieving low power consumption at lower voltage levels, Design with ultra-low voltage MOSFET arrays.

Number 9 is the kick-off article in a three-part series, Developing an automotive electrical distribution system: Part 1 ” System design, which keyed on efficiency in design and the ever shortening design cycle for automotive systems.

Number 8 discusses touch sensors and the choices they give design engineers, Capacitive touch switches boost automotive interface options.

Number 7 begins a series on electric motor control, Implement embedded speed control for brushless DC motors: Part 1.

Number 6 is one of our popular Toyota Prius teardown articles, Inside the Toyota Prius: Part 5 – Inverter/converter is Prius’ power broker.

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