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The blocking test for DCS1800 is performed by applying a GMSK modulated desired signal 3dB above the required receiver reference sensitivity. Then a single unmodulated tone is applied to the receiver at discrete increments of 200KHz from the desired signal with a magnitude shown in Table 4.

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The blocking test for DCS1800 is performed by applying a GMSK modulated desired signal 3dB above the required receiver reference sensitivity. Then a single unmodulated tone is applied to the receiver at discrete increments of 200KHz from the desired signal with a magnitude shown in Table 4.

SHANGHAI, China — Taiwan's Silicon Integrated Systems unveiled its first wireless LAN chip on Monday (March 17), fielding a media access controller for 802.11b networks.

The launch of the SiS160 should not be seen as just a tentative step into this rapidly emerging market. It is a confident leap forward and demonstrates the priority that SiS places on developments for the WLAN market and 802.11b as the solution of the moment,” SiS President Michael Chen said in a statement.

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SiS may need every ounce of resolve it can muster to survive in the 802.11b market. In Taiwan alone there are numerous companies trying to cash in on the market, including Realtek Semiconductor, ADMtek, Gemtek and InProcomm. Multinationals such as Intersil, Intel and RF Micro Devices are also in on the game.

Indeed, the timing of SiS' WLAN chip launch coincides with a massive marketing campaign by Intel to increase awareness of WLANs, thus spurring demand for its new wireless-oriented Centrino platform.

Shipments of 802.11 chipsets, including all 11x variants, should grow 80 percent in 2003 to about 35 million units, according to IC Insights. From 2002 to 2006, annual growth is expected to hit 50 percent.

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The market researcher has questioned, however, whether there are too many suppliers jumping on the bandwagon. In a recent report, the firm noted more than 50 companies supply the market, which seems to be an excessive number of companies jumping into the fray. Given that, there is bound to be some consolidation among companies and some that succumb to competitive pressures.”

SiS already has several key partners” designing in the new chip and is ready to ramp up volume production on a 0.18-micron process. The chip comes in a 128-pin LQFP (low-profile quad flat pack) package, has power saving modes to extend battery life and its host interface includes support for PCI, MiniPCI and Cardbus.

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The SiS160 chip has already been certified to conform with [U.S. Federal Communications Commission] regulations and, with support for the different channel requirements in North America, Japan and Europe built into the driver, the SiS160 is a solution ready for wireless operation anywhere in the world,” Chen said.

The SiS160 also includes standard support for both 64- and 128-bit data encryption using the WEP (wired equivalent privacy) algorithm. In addition, SiS has added security features that encompass TKIP (temporal key integrity protocol) and WPA (Wi-Fi protected access).

This type of memory offers the performance and storage capacity needed to support leading-edge applications ranging from games to networking infrastructure equipment. High-performance embedded DRAM enables throughput into the gigabit-per-second range as well as compact designs with modest power dissipation in office, industrial equipment and lightweight electronic devices.

As a reliable, proven and compiled memory technology, embedded SRAM is often the default choice for embedded memory solutions. Unfortunately, embedded SRAM has drawbacks that become an issue as feature sizes shrink and integration increases. First, embedded SRAM is not dense because it requires the conventional six transistors to form a single bit cell. Reasonable SRAM sizes are thus less than 1 megabit. Second, embedded SRAM dissipates more power than alternative technologies. Embedded SRAM is also proving to be increasingly susceptible to soft errors caused by high-energy particles.

Alternatively, embedded DRAM provides higher density, lower power consumption and lower soft error rate (SER). Several types of DRAM technology have been developed, and they fall into three categories: commodity DRAM, standard logic (SL) and merged logic (ML). The first type is the technology used to fabricate discrete commodity DRAM, while both the SL and ML types use standard CMOS.

The difference between SL- and ML-type embedded DRAM is in the DRAM capacitor structures. SL-type DRAM implements planar capacitors (between the well and gate-poly). The ML type uses DRAM capacitors similar to the commodity DRAM type, but the fabrication technology must be completely different from that of commodity DRAM. Both DRAM-type and ML-type embedded DRAM use one of two alternative capacitor structures: stacked or trench.

The commodity DRAM process offers high memory density resulting from its small memory cell size. However, this type of DRAM does not suit high-speed applications because of its lower transistor performance and limited number of metal layers. Some DRAM-type processes can enhance transistor performance, but with a huge number of additional process steps.

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