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5X35023B-003NXGI_Datasheet PDF

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Le secteur de la propriété intellectuelle a également dû abandonner l’idée, selon laquelle la propriété intellectuelle est écrite puis mise sous licence à des tiers. « Nous attendons avec impatience que la propriété intellectuelle se fige. Pour nous, elle est un partenariat qui peut être observé quotidiennement. Pour la plus grande partie des systèmes sur puce, les cœurs de propriété intellectuelle sont écrits en même temps que les systèmes sur puce sont conçus ».

« Seul un lien étroit entre les ingénieurs de procédés, de conception et au niveau système permettra des systèmes sur puce entièrement normalisés », conclut M. Magarshack.

5X35023B-003NXGI_Datasheet PDF

Signal processing applications are becoming more complicated, and so are the processors that run them. As a result, application developers rely on compilers and other tools more heavily than ever. This has made tools a decisive factor in processor-selection decisions. Indeed, differences in tools are a central consideration when choosing between a digital signal processor (DSP) and a general-purpose processor (GPP).

DSP vendors often take a go-it-alone approach when it comes to tools: In many cases, the only tool set available for a DSP is the vendor’s internally developed tool set. In contrast, GPP vendors often pay two or more third-party tool vendors to develop tool sets. And if the GPP is popular enough, tool providers will develop tools on their own initiative. As a result, developers using typical GPPs can choose from a wide selection of tools.

Although it expands users’ choices, paying a third party vendor to develop tools has some disadvantages. The processor vendor has a uniquely deep understanding of the processor. The processor vendor is also likely to have a superior understanding of its target applications and its customers’ needs. Both types of knowledge enable the processor vendor to optimize the tools in ways that third-party vendors would not, and to include useful features that third-party vendors would not. This is particularly true for DSP vendors, whose processors, target applications, and customers are typically specialized in some way.

5X35023B-003NXGI_Datasheet PDF

On the other hand, there is little room for differentiation in generic tool components such as the compiler front-end, and processor vendors usually have no special expertise in these components. For such components, third-party offerings are often superior—and tool providers can often create these components faster than the processor vendor can.

Given these tradeoffs, it is not surprising that a few processor vendors are now mixing elements from these two approaches. In this hybrid approach, the processor vendor develops the tool components that benefit most from processor- and application-specific optimizations, such as the compiler back-end. Meanwhile, the third-party vendor focuses on the more generic components like the compiler front-end.

5X35023B-003NXGI_Datasheet PDF

As tools become more important, processor vendors targeting signal-processing applications must take a hard look at their tool-development strategies. Ideally, their tools should offer the specialized features traditionally associated with DSP tools and the broad range of options traditionally associated with GPP tools. For many vendors, the best way to achieve both goals is to use a hybrid approach.

Atascadero, Calif.—Communications computer board maker Gateworks Corp . is adding a new member to its existing Avila line of networking boards. Packing its own input-voltage DC-to-DC converter, this latest board should find a home in designs of wired and wireless network routers, backhaul repeaters, switches, bridges, access points, and concentrators. It will also operate from 6-V to 28-V DC sources, and it dissipates about 4-W of power.

The Lattice partners program is designed to allow customers to easily access and integrate approved third-party IP products using Lattice programmable devices. Partner IP support for our new FPGA families continues to grow rapidly,” said Kopec. We're pleased to continue our partnerships with CAST, DCD and Eureka Technology, and very excited by the increased IP core performance that each has achieved using our new ispLEVER design tool software.”CAST (http://www.cast-inc.com/) IP cores for the LatticeECP and LatticeEC devices include CAN Bus and 1394a functions. DCD (http://www.dcd.pl/) provides a variety of microprocessor and peripheral functions, including 8051 and PIC compatible microprocessors. Eureka Technology (http://www.eurekatech.com.) provides a variety of bus interface functions and a CompactFlash/PCMCIA Host Adapter IP.

Lattice also has free reference designs now available for the LatticeECP and LatticeEC devices to support functions including:

QDR II SDRAM Controller SDR SDRAM Controller I2C Bus Master Controller 1553 Data Bus Encoder/Decoder RGMII Bridge

About the LatticeECP-DSP and LatticeEC FPGA Families

Announced June 28, 2004, the LatticeECP-DSP and LatticeEC FPGA device families are architected to provide the most optimized feature sets combined with the lowest total solution costs of any FPGAs. The new LatticeECP-DSP products, targeted for high-performance DSP applications, provide up to a 50% performance and 75% logic utilization improvement over other low-cost solutions when implementing common DSP functions. The LatticeEC FPGA product family, targeted for general-purpose FPGA applications, is a precise and targeted response to the market's explosive demand for low-cost, architecturally streamlined logic solutions. Through advanced 130nm silicon technology, an optimized architecture and proprietary circuit design, the new Lattice devices lower total solution costs by up to 30% to 50% compared with existing FPGA solutions, and are expected to broaden the adoption of FPGAs within the $20 billion ASIC marketplace.

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